Optimization of Phase-Locked Loop Circuits via Geometric Programming

D. Colleran, C. Portmann, A. Hassibi, C. Crusius, S. Mohan, S. Boyd, T. Lee, and M. Hershenson

Proceedings of the Custom Integrated Circuits Conference (CICC), p377-380, San Jose, Sept. 2003.

We describe the global optimization of phase-locked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a 0.18um, 1.8V CMOS process. Silicon measurements show good agreement with the model. The results include a 1.9GHz PLL with a period jitter of 2.2ps RMS and an accumulated jitter of 6.2ps RMS, consuming 10.8mW.